The present invention relates to a packet exchange data transmission system, and more particularly to a packet exchange data transmission system suitable to an ultra high speed data transmission between packet exchangers.
In a data transmission between packet exchangers in a prior art packet exchange data transmission system, a high level data control (HDLC) procedure and a packet level control procedure are adopted in accordance with a CCITT standard protocol and it is usually implemented by a programmable data processing system.
FIG. 1 shows a configuration of a packet exchange network having three packet exchangers, and FIG. 2 shows a basic data format of a data packet transmitted through a line.
A packet terminal 1 transmits a data packet having a format as shown in FIG. 2 to a packet exchanger 3 through a subscriber line 2, the packet exchanger 3 transmits the packet to a packet exchanger 5 or a packet exchanger 9 through a trunk circuit 4 or a trunk circuit 8, the packet exchanger 5 transmits the packet data received through the trunk circuit 4 or the trunk circuit 10 to a packet terminal 7 in the format shown in FIG. 2 through a subscriber line 6, and the packet terminal 7 is similar to the packet terminal 1.
The format of the packet data transmitted through the subscriber line 2 or 6 comprises, as shown in FIG. 2, four fields, that is, a user data 24, a packet header 23 which is used in the packet level control procedure and contains destination information of the packet, a data link control (DLC) header 21 used in the HDLC procedure and a data link control (DLC) trailer 22. In the HDLC procedure, the DLC header 21 comprises a flag (F) indicating a beginning of frame, an information indicating a transmission direction of the frame and a control (C) indicating a type and a sequence of the frame. The DLC trailer 22 comprises a data error check code FCS (frame check sequence) and a flag (F) indicating an end of frame. The data error check code (FCS) is an error check information generated, under a certain logic, based on information excluding the flags (F) indicating the beginning and the end of the frame and the data error check code (FCS). The packet header 23 and the user data 24 are collectively referred to as a data packet, and the data packet, the DLC header and the DLC trailer are collectively referred to as a frame.
The packet exchanger 3 checks the FCS of the frame including the data packet received from the packet terminal 1 and detects a data error between the packet terminal 1 and the packet exchanger 3. It also checks the sequence information contained in the control C to detect a loss of frame. When it detects the data error or the loss of frame, it sends a negation response to the packet terminal 1 in accordance with the HDLC procedure and request retransmission of the data. When the packet exchanger 3 normally receives the frame, it selects a path by the destination information contained in the packet header 23 and sends the data packet in the frame format shown in FIG. 2 to the packet exchanger 5 connected to the packet terminal 7. The packet exchanger 3 modifies a portion of the frame such as the destination information contained in the packet header 23, reconstructs the FCS and sends the data package to the trunk circuit 4. The packet exchanger 5 checks the FCS and the sequence of the control C of the received frame, identifies the packet terminal 7 by the destination information contained in the packet header 23 and sends the data packet to the packet terminal 7.
When the trunk circuit 4 cannot be used by an obstacle, the packet exchanger 5 sends the data packet to the packet terminal 7 through the trunk circuit 8, the packet exchanger 9 and the trunk circuit 10. Accordingly, the packet exchanger does not always receive the data packet in the same order as the packet terminal 1 transmits the data packet, and the packet exchanger 5 rearranges the packet data in accordance with the packet sequence information C contained in the packet header 23.
In the past, the packet exchangers 3, 5 and 9 were implemented by a single programmable processor, but as the development of the microprocessor, they are recently constructed by a plurality of processors. FIG. 3 shows a prior art packet switching network comprising the packet exchanger 3 and the packet exchanger 5.
In FIG. 3, a packet exchanger 103 has a plurality of main controllers 132 and 134 interconnected by a high speed interface 133 which is a common transmission line, and the subscriber line 2 and the trunk circuit 4 are connected to the main controllers 132 and 134 through communication controllers 131 and 135, respectively. The main controller 132 is a subscriber line processor and the main controller 134 is a trunk circuit processor. The preparation and check of the FCS in accordance with the HDLC procedure are carried out by the communication controllers 131 and 135, and the sequence control and the recovery procedure for the error are carried out by the main controllers 132 and 134. The control of the packet level procedure is carried out by the main controllers 132 and 134. The operation of the packet exchanger 105 is identical to that of the packet exchanger 103. The main controllers 132 and 134 are usually microprocessors whose processing steps are at least 2-5 K steps per packet which comprises 100 bytes in average. Assuming that the microprocessor has a processing ability of 1 microsecond per step and a utilization factor is 100%, a maximum transmission rate is 160-400 K bits/second. Taking competition in the high speed interface 133 and the utilization factor of the main controllers 132 and 134 into consideration, a practical transmission rate is 64 K bits/second at maximum unless the performance of the microprocessor is significantly improved.
However, as the communication technology is developed, a line service at a transmission rate of several mega-bits/second or several hundreds mega-bits/second for an optical fiber line is expected, and such an ultra high speed line will be used in the packet switching network as the trunk circuit.
In order to increase the transmission rate of the trunk circuit 4, the use of multiplexors 41 and 42 (FIG. 4) has been proposed. In FIG. 4, the multiplexers 41 and 42 are used so that data on a plurality of low speed lines 43 and 44 are multiplexed onto a high speed trunk circuit 4' instead of the trunk circuit 4 of FIG. 3. In this system, since the plurality of low speed lines 43 and 44 are used, n main controllers 134-1, . . . 134-n and 154-1, . . . 154-n are used instead of the main controller 134. The number of the main controlles is determined by the transmission rate of the low speed line 43 or 44 and the performance of the main controller. In FIG. 4, the subscriber line main controllers 132 and 152 to which the subscriber lines 2 and 6 are connected are omitted, although they are actually connected as shown in FIG. 3. This system has the following disadvantages.
(1) The number of main controllers increases and this leads to the increase of the size and cost of the packet exchanger. For example, when the data transmission rate of one main controller is 64 K bits/second, the transmission rate of the trunk circuit shown in FIG. 3 is 64 K bits/second, the transmission rate of the low speed lines 43 and 44 are 64 K bits/second and the transmission rate of the trunk circuit 4' is 384 K bits/second, then six main controllers are required to maintain the transmission rate of the trunk circuit 4'.
(2) The transmission rate of the trunk circuit 4' is increased and a throughput is improved, but when the trunk circuit 4' is used in a time slot allocation time-division fashion, the transmission rate of the trunk circuit 4' is increased up to only 64 K bits/second so long as the communication between the packet terminals 1 and 7 is concerned, and it does not significantly differ from the transmission rate of the trunk circuit 4 shown in FIG. 3. Accordingly, a response time between the packet terminals 1 and 7 is not significantly improved over that of the system shown in FIG. 3.
(3) When the time division system in the multiplexer 41 is such that a time slot is periodically allotted to each of the low speed lines 43, non-used time slots may exist depending on a traffic of packets handled by the main controllers 134-1, . . . 134-n, and the utilization factor of the trunk circuit 4' is not improved.
In the system shown in FIG. 3, even if the number of trunk circuits 4 is increased and the number of main controllers 134 is increased accordingly, the problems of (1) and (2) are not resolved.